This application claims priority from Korean patent application No. 2000-69533 filed Nov. 22, 2000 which is incorporated by reference.
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a scheme for storing an address of a defective memory cell.
2. Description of the Related Art
For many integrated circuit memory arrays, several redundant rows or columns are provided to be used as substitutes for defective rows or columns of main memory cells. When a defective row or column is identified, rather than treating the entire chip as defective, a redundant row or column can be employed instead of the defective row or column. The redundant row or column corresponding to the defective row or column is assigned for replacing the defective row or column. Then, when an address corresponding to the defective row or column is provided, the redundant row or column is accessed instead.
For the purpose of replacing the defective row or column with the redundant row or column, the memory device includes a defective address storage circuit (or, defective address detection circuit). The defective address storage circuit monitors row/column addresses and enables the redundant row or column in place of the defect row or column when the defective row or column address is provided. Some defective address storage circuits are disclosed in U.S. Pat. No. 5,258,953 entitled xe2x80x9cSemiconductor Memory Devicexe2x80x9d, U.S. Pat. No. 5,657,280 entitled xe2x80x9cDefective Cell Repairing Circuit and Method of Semiconductor Memory Devicexe2x80x9d, and U.S. Pat. No. 5,723,999 entitled xe2x80x9cRedundant Row Fuse Bank Circuitxe2x80x9d.
FIG. 1 is a circuit diagram showing a prior art defective address storage circuit. The circuit of FIG. 1 includes a fuse 11, P-channel metal oxide semiconductor (MOS) transistor 12, inverter 13, and NOR-type fuse bank (or, NOR-type fuse array) 30. The fuse 11 and the PMOS transistor 12 are connected between a power supply voltage and a node NO, and the PMOS transistor 12 is switched on/off in response to a signal nRchk. An input terminal of the inverter 13 is connected to node NO, and an output terminal thereof provides a signal nRcen. The NOR-type fuse bank 30 includes fuses 14 through 24, and N-channel MOS transistors 15xcx9c25 which correspond to fuses 14 through 24, respectively. As shown in FIG. 1, the fuses 14xcx9c24 and the NMOS transistors 15xcx9c25 are arranged in a NOR architecture.
If no defective cells are identified, fuse 11 is blown and fuses 14xcx9c24 of the fuse bank 30 remain connected. In this state, at least one of the NMOS transistors 15xcx9c25 is turned on regardless of the combination of address signals A0, nA0, A1, nA1, A2, and nA2 provided, so the signal at node N0 remains low.
If, however, a defective row or column is identified, fuse 11 is left in the connected state, and fuses 14xcx9c24 of the fuse bank 30 are selectively cut to detect the address corresponding to the defective row or column. For example, if the address of a defective row or column is indicated by address signals A0xcx9cA2 being low, then fuses 14, 18, and 22 are left connected, while fuses 16, 20, and 24 are cut. Thus, when address signals A0xcx9cA2 are low (and address signals nA0xcx9cnA2 are high), node NO is charged to the high level through fuse 11 and PMOS transistor 12 because all current paths from node NO to ground are cut off. The signal nRcen is driven low by the inverter 13, which indicates that the row or column of the current address has a defect.
The signal nRcen causes the defective row or column to be replaced with the corresponding redundant row or column. When address signals corresponding to a normal row or column are provided, at least one of the address signals A0xcx9cA2 is high, so the NMOS transistor corresponding thereto is turned on. Thus, a current path is created from node N0 to the ground voltage terminal. Since the current drive capability of the PMOS transistor 12 is set lower than that of the NMOS transistors of the fuse bank 30, the node N0 is maintained at the low level, thereby causing the signal nRcen to go high.
Memory devices typically include multiple defective address storage circuits. As described above, each of the defective address storage circuits creates a direct current path from the power supply voltage to the ground voltage when the address provided from the outside is not identical with the stored address of the defective address storage circuit. This results in unnecessary current consumption.
The present invention involves the use of address storage blocks coupled in series to reduce current consumption in a defective address storage circuit for a semiconductor memory device.
One aspect of the present invention is a defective address storage circuit for a semiconductor memory device having redundant cells for replacing defective memory cells, the circuit comprising: a precharge circuit coupled between a first voltage terminal and an output node and adapted to precharge the output node to a potential of the first voltage terminal in response to a control signal; and a fuse bank coupled between the output node and a second voltage terminal and adapted to store address signals corresponding to a defective memory cell; wherein the fuse bank comprises address storage blocks coupled in series between the output node and the second voltage terminal.
Another aspect of the present invention is a defective address storage circuit for a semiconductor memory device comprising a plurality of address storage blocks coupled in series.
A further aspect of the present invention is a defective address storage circuit for a semiconductor memory device comprising: means for precharging an output node; and a plurality of means for storing a defective address coupled in series with the output node.